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acpl-m75l single-channel high speed 15 mbd cmos optocoupler with glitch-free power-up feature data sheet caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. description the acpl-m75l (single-channel) is 15 mbd cmos opto- couplers in soic-5 package. the optocouplers utilize the latest cmos ic technology to achieve outstanding per- formance with very low power consumption. basic build- ing blocks of acpl-m75l are high speed leds and cmos detector ics. each detector incorporates an integrated photodiode, a high speed transimpedance amplifi er, and a voltage comparator with an output driver. component image lead (pb) free rohs 6 fully compliant rohs 6 fully compliant options available; -xxxe denotes a lead-f r ee p r oduct features ? +3.3v and +5 v cmos compatibility ? 25ns max. pulse width distortion ? 55ns max. propagation delay ? 40ns max. propagation delay skew ? high speed: 15 mbd min ? 10 kv/s minimum common mode rejection ? C40 to 105c temperature range ? glitch-free power-up feature ? safety and regulatory approvals: - ul recognized: 3750 v rms for 1 min. per ul 1577 - csa component acceptance notice #5 - iec/en/din en 60747-5-2 approved option 060 applications ? digital fi eld bus isolation: - rs485, rs232, canbus ? multiplexed data transmission ? computer peripheral interface ? microprocessor system interface ? dc/dc converter ? servo motor truth table led v o , output off h on l a 0.1uf bypass capacitor must be connected between pins 4 and 6. acpl - m75l 1 3 6 4 5 ano d e ca t ho d e v dd g n d vo s hi eld
2 ordering information acpl-m75l will be ul recognized with 3750 vrms for 1 minute per ul1577. part number option package surface mount g ull wing tape& reel ul 5000 vrms/ 1 minute rating iec/en/din en 6 07 4 7-5-2 quantity rohs compliant acpl-m75l -000e so-5 x 100 per tube -500e x x 1500 per reel -060e x x 100 per tube -560e x x x 1500 per reel to order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. example 1: ACPL-M75L-500E to order product of small outline so-5 package in tape and reel packaging in rohs compliant. example 2: acpl-m75l-000e to order product of small outline so-5 package in tube packaging and in rohs compliant. option datasheets are available. contact your avago sales representative or authorized distributor for information.
3 package dimensions acpl-m75l (jedec mo-155 package) mxxx xxx 6 5 4 3 1 7.0 0.2 (0.276 0.008) 2.5 0.1 (0.098 0.004) 0.102 0.102 (0.004 0.004) v cc v out gnd cathode anode 4.4 0.1 (0.173 0.004) 1.27 (0.050) bsc 0.216 0.038 (0.0085 0.0015) 0.71 (0.028) min 0.4 0.05 (0.016 0.002) 3.6 0.1* (0.142 0.004) dimensions in millimeters (inches) * maximum mold flash on each side is 0.15 mm (0.006) note: floating lead protrusion is 0.15 mm (6 mils) max. 7 max. max. lead coplanarity = 0.102 (0.004) 8.27 (0.325) 2.0 (0.080) 2.5 (0. 1 0) 1 .3 (0.05) 0.64 (0.025) 4.4 (0. 1 7) dim en si on s i n mi ll im eter s and (i nche s) lan d pattern recommen d ation
4 sol d er refl ow thermal profi le 0 ti me (seconds) t empera t ure (c) 200 1 00 50 1 50 1 00 200 250 300 0 30 sec. 50 sec. 30 sec. 1 60c 1 40c 1 50c pea k t emp. 245c pea k t emp. 240c pea k t emp. 230c solder i ng ti me 200c pre h ea ti ng ti me 1 50c , 90 + 30 sec. 2.5 c 0.5 c / sec. 3 o c + 1 c /C 0.5c ti g ht t yp i cal loose room t empera t ure pre h ea ti ng ra t e 3c + 1 c /C 0.5c / sec. re f lo w h ea ti ng ra t e 2.5c 0.5c / sec. recommen d e d pb-free ir flow 2 1 7 c ramp - do w n 6 c / sec. max. ramp - up 3 c / sec. max. 1 50 - 200 c 260 + 0 /- 5 c t 25 c to pea k 60 to 1 50 sec. 20 - 40 sec. ti me withi n 5 c of ac t ual pea k t empera t ure t p t s pre h ea t 60 to 1 80 sec. t l t l t smax t smin 25 t p ti me t empera t ure n ote s: the t im e fro m 2 5 c to peak te m perature = 8 mi nute s m ax . t sm ax = 2 00 c , t smi n = 1 50 c n on-hal i de flux s hould be u s ed regulatory information the acpl-m75l has been approved by the following organizations: non-halide fl ux should be used. ul recognized under ul 1577, component recognition program, file e55361. csa approved under csa component acceptance notice #5, file ca88324. iec/en/din en 6 07 4 7-5-2 approved under: iec 60747-5-2:1997 + a1:2002 en 60747-5-2:2001 + a1:2002 din en 60747-5-2 (vde 0884teil 2):2003-01 (option 060 only)
5 insulation an d safety relate d specifi cations parameter symbol value units con d itions minimum external air gap (clearance) l(i01) 5 mm measured from input terminals to output terminals, shortest distance through air. minimum external tracking (creepage) l(i02) 5 mm measured from input terminals to output terminals, shortest distance path along body. minimum internal plastic gap (internal clearance) 0.08 mm insulation thickness between emitter and detector; also known as distance through insulation. tracking resistance (comparative tracking index) cti 175 volts din iec 112/vde 0303 part 1 isolation group iiia material group (din vde 0110, 1/89, table 1) all avago technologies data sheets report the creepage and clearance inherent to the optocoupler component it- self. these dimensions are needed as a starting point for the equipment designer when determining the circuit insulation requirements. however, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specifi ed for individual equipment standards. for creepage, the shortest distance path along the surface of a printed circuit board between the solder fi llets of the input and output leads must be considered. there are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. creep- age and clearance distances will also change depending on factors such as pollution degree and insulation level. iec/en/din en 6 07 4 7-5-2 insulation relate d characteristics (option 0 6 0) description symbol option 0 6 0 units installation classifi cation per din vde 0110/1.89, table 1 for rated mains voltage 150 v rms for rated mains voltage 300 v rms i-iv i-iii climatic classifi cation 55/105/21 pollution degree (din vde 0110/1.89) 2 maximum working insulation voltage v iorm 560 v peak input to output test voltage, method b? v iorm x 1.875 = v pr , 100% production test with t m = 1 sec, partial discharge < 5 pc v pr 1050 v peak input to output test voltage, method a? v iorm x 1.5 = v pr , type and sample test, t m = 60 sec, partial discharge < 5 pc v pr 840 v peak highest allowable overvoltage? (transient overvoltage, t ini = 10 sec) v iotm 4000 v peak safety limiting values (maximum values allowed in the event of a failure, also see thermal derating curve, figure 11.) case temperature input current output power t s i s, input ps ,output 150 150 600 c ma mw insulation resistance at t s , v 10 = 500 v r io 10 9
6 absolute maximum ratings parameter symbol min. max. units storage temperature t s C55 +125 c ambient operating temperature t a C40 +105 c supply voltages v dd 0 6.0 volts output voltage v o C0.5 v dd +0.5 volts average forward input current i f - 10.0 ma average output current i o - 10.0 ma lead solder temperature 260c for 10 sec., 1.6 mm below seating plane solder refl ow temperature profi le see solder refl ow temperature profi le section recommen d e d operating con d itions parameter symbol min. max. units ambient operating temperature t a C40 +105 c supply voltages v dd 4.5 5.5 v 3.0 3.6 v input current (on) i f 48ma forward input voltage (off) v f(off) 0 0.8 v supply voltage slew rate [1] s r 0.5 500 v/ms electrical specifi cations over recommended temperature (t a = C40c to +105c), 3.0v v dd 3.6v and 4.5 v v dd 5.5 v. all typical specifi cations are at t a =+25c, v dd = +3.3v. parameter symbol min. typ. max. units test con d itions input forward voltage v f 1.3 1.5 1.8 v i f = 6ma input reverse breakdown voltage bv r 5.0 v i r = 10 a logic high output voltage v oh v dd -1 v dd -0.3 v i f = 0, i o = -4 ma, v dd =3.3v v dd -1 v dd -0.2 v i f = 0, i o = -4 ma, v dd =5v logic low output voltage v ol 0.2 0.8 v i f = 6ma, i o = 4ma, v dd =3.3v 0.35 0.8 v i f = 6ma, i o = 4ma, v dd =5v input threshold current i th 1 3 ma i ol = 20 a logic low output supply current i ddl 4.5 6.5 ma i f = 6 ma logic high output supply current i ddh 4 6 ma i f = 0
7 switching specifi cations over recommended temperature (t a = C40c to +105c), 3.0v v dd 3.6v and 4.5 v v dd 5.5 v. all typical specifi cations are at t a =+25c, v dd = +3.3v. parameter symbol min. typ. max. units test con d itions propagation delay time to logic low output [2] t phl 25 55 ns i f = 6ma, c l = 15pf cmos signal levels propagation delay time to logic high output [2] t plh 21 55 ns i f = 6ma, c l = 15pf, cmos signal levels pulse width t pw 66.7 ns pulse width distortion [3] |pwd | 0 4 25 ns i f = 6ma, c l = 15pf, cmos signal levels propagation delay skew [4] t psk 40 ns i f = 6ma, c l = 15pf cmos signal levels output rise time (10% C 90%) t r 3.5 ns i f = 6ma, c l = 15pf cmos signal levels output fall time (90% - 10%) t f 3.5 ns i f = 6ma, c l = 15pf cmos signal levels common mode transient immunity at logic high output [5] | cmh | 10 15 kv/s v cm = 1000 v, t a = 25c, i f = 0 ma (figure 18) 30 35 kv/s using avagos application circuit (figure 13) common mode transient immunity at logic low output [6] | cml | 10 15 kv/s v cm = 1000 v, t a = 25c, i f = 6 ma (figure 18) 30 35 kv/s using avagos application circuit (figure 13) package characteristics all typical at t a = 25 c. parameter symbol min. typ. max. units test con d itions input-output insulation i i-o 1.0 a 45% rh, t = 5 s v i-o = 3 kv dc, t a = 25c input-output momentary withstand voltage v iso 3750 vrms rh 50%, t = 1 min., t a = 25c input-output resistance r i-o 10 12 ? v i-o = 500 v dc input-output capacitance c i-o 0.6 pf f = 1 mhz, t a = 25c notes: 1. slew rate of supply voltage ramping is recommended to ensure no glitch more than 1v to appear at the output pin. 2. t phl propagation delay is measured from the 50% v dd level on the rising edge of the input pulse to the 50% v dd level of the falling edge of the v o signal. t plh propagation delay is measured from the 50% v dd level on the falling edge of the input pulse to the 50% v dd level of the rising edge of the v o signal. 3. pwd is defi ned as |t phl - t plh |. 4. t psk is equal to the magnitude of the worst case diff erence in t phl and/or t plh that will be seen between units at any given temperature within the recommended operating conditions. 5. cm h is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state. 6. cm l is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state.
8 v f -f or w ard vol t age - v i f -f or w ard curren t-m a t a -t empera t ure - o c i dd h - log i c hi g h ou t pu t supply curren t -m a t a -t empera t ure - o c i th -i npu t th res h old curren t-m a t a -t empera t ure - o c i ddl - log i c lo w ou t pu t supply curren t-m a 0.0 1 0. 1 1 1 0 1 .2 1 .3 1 .4 1 .5 1 .6 t a = 25c i f v f 0.000 0.200 0.400 0.600 0.800 1 .000 1 .200 1 .400 1 .600 - 40 - 20 0 20 40 60 80 1 00 1 20 5v 3.3v i o l = 20 u a 0 1 2 3 4 5 6 - 40 - 20 0 20 40 60 80 1 00 v dd = 5v v dd = 3.3v 0 1 2 3 4 5 6 - 40 - 20 0 20 40 60 80 1 00 v dd = 5.0v v dd = 3.3v figure 1. typical input d io d e forwar d characteristic. figure 2. typical input threshol d current vs. temperature. figure 3 . typical logic high o/p supply current vs. temperature. figure 4 . typical logic low o/p supply current vs. temperature. figure 5. typical switching spee d vs. pulse input current at 5v supply voltage. figure 6 . typical switching spee d vs. pulse input current at 3 . 3 v supply voltage. i f C pu l s e i npu t curr e n t C ma t p C propaga ti on d el a y; pwd - pu l s e w i d th d i s t or ti on C ns i f C pu l s e i npu t curr e n t C ma t p C propaga ti on d el a y; pwd - pu l s e w i d th d i s t or ti on C ns 0 5 1 0 1 5 20 25 30 35 4 5 6 7 8 v dd = 5 v t a = 25 c t p hl t p lh pwd 0 5 1 0 1 5 20 25 30 35 4 5 6 7 8 v dd = 3.3 v t a = 25 c t p hl t p lh pwd
9 application information bypassing an d pc boar d layout the acpl-m75l optocoupler is extremely easy to use. acpl-m75l provides cmos logic output due to the high- speed cmos ic technology used. the external components required for proper operation are the input limiting resistor and the output bypass ca- pacitor. capacitor values should be between 0.01 f and 0.1 f. for each capacitor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed 20 mm. figure 8. recommen d e d printe d circuit boar d layout figure 7. typical v f vs. temperature. propagation delay, pulse-wi d th distortion an d propa- gation delay skew propagation delay is a fi gure of merit which describes how quickly a logic signal propagates through a system. the propagation delay from low to high (t plh ) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. similarly, the propagation delay from high to low (t phl ) is the amount of time required for the input signal to propa- gate to the output, causing the output to change from high to low (see figure 9). figure 9. propagation d elay an d skew waveform figure 10. parallel d ata transmission example data inputs clock data outputs clock t psk t psk 50% 50% t psk i f v o i f v o 2.5 v, cmos 2.5 v, cmos 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 - 40 -20 0 20 40 60 80 100 t a - temperature - o c v f - forward voltage - c 5 4 3 1 2 i in v dd2 v o gnd2 xxx yww c c = 0.01 uf to 0.1uf gnd1
10 pulse-width distortion (pwd) results when t plh and t phl diff er in value. pwd is defi ned as the diff erence between t plh and t phl and often pwd determines the maximum data rate capability of a transmission system. pwd can be expressed in percent by dividing the pwd (in ns) by the minimum pulse width (in ns) being transmitted. typically, pwd on the order of 20-30% of the minimum pulse width is tolerable; the exact fi gure depends on the particular ap- plication (rs232, rs422, t-1, etc.). propagation delay skew, t psk , is an important parameter to consider in parallel data applications where synchroni- zation of signals on parallel data lines is a concern. if the parallel data is being sent through a group of opto- couplers, diff erences in propagation delays will cause the data to arrive at the outputs of the optocouplers at diff er- ent times. if this diff erence in propagation delays is large enough, it will determine the maximum rate at which par- allel data can be sent through the optocouplers. propagation delay skew is defi ned as the diff erence be- tween the minimum and maximum propagation delays, either t plh or t phl , for any given group of optocouplers which are operating under the same conditions (i.e., the same supply voltage, output load, and operating temper- ature). as illustrated in figure 10, if the inputs of a group of optocouplers are switched either on or off at the same time, t psk is the diff erence between the shortest propaga- tion delay, either t plh or t phl , and the longest propagation delay, either t plh or t phl . as mentioned earlier, t psk can de- termine the maximum parallel data transmission rate. figure 10 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. the fi gure shows data and clock signals at the inputs and outputs of the optocou- plers. to obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. propagation delay skew represents the uncertainty of where an edge might be after being sent through an opt- ocoupler. figure 10 shows that there will be uncertainty in both the data and the clock lines. it is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. from these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice t psk . a cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem. the t psk specifi ed optocouplers off er the advantages of guaranteed specifi cations for propagation delays, pulse- width distortion and propagation delay skew over the rec- ommended temperature, and power supply ranges. figure 11. connection of peaking capacitor (cpeak) in parallel of the input limiting resistor (rlimit) to improve spee d performance figure 12. improvement of tp an d pwd with a dd e d 100pf peaking capacitor in parallel of input limiting resistor. 0 5 10 15 20 25 30 35 -40 -20 0 20 40 60 80 100 t phl t plh t plh t phl |pwd| with peaking cap without peaking cap 0 5 10 15 20 25 30 35 40 -40 -20 0 20 40 60 80 100 t phl t plh t phl t plh |pwd| with peaking cap without peaking cap (ii) v dd = 3 . 3 v, c peak =100pf, r limit =250 (i) v dd =5v, c peak =100pf, r limit =5 3 0 gnd 2 v dd2 0.1 f gnd 1 r limit shiel v in + - c peak v o r drv = 50 shield + -
11 table 1. eff ects of common mo d e pulse direction on transient i led if d v cm / d t is: then i lp flows: an d i ln flows: if |i lp | < |i ln |, led i f current is momentarily: if |i lp | > |i ln |, led i f current is momentarily: positive (>0) away from led anode through c la away from led cathode through c lc increased decreased negative (<0) toward led anode through c la toward led cathode through c lc decreased increased powering sequence v dd needs to achieve a minimum level of 3v before pow- ering up the output connecting component. input limiting resistors acpl-m75l is direct current driven (figure 8), and thus eliminate the need for input power supply. to limit the amount of current fl owing through the led, it is recom- mended that a 530ohm resistor is connected in series with anode of led (i.e. pin 1 for acpl-m75l) at 5v input signal. at 3.3v input signal, it is recommended to connect 250 resistor in series with anode of led. the recommended limiting resistors is based on the assumption that the driv- er output impedence is 50 (as shown in figure 11). spee d improvement a peaking capacitor can be placed across the input cur- rent limit resistor (figure 11) to achieve enhanced speed performance. the value of the peaking cap is dependent to the rise and fall time of the input signal and supply volt- ages and led input driving current (i f ). figure 12 shows signifi cant improvement of propagation delay and pulse with distortion with added peak capacitor at driving cur- rent of 6ma for both 3.3v and 5v power supply. common mo d e rejection for acpl-m75l figure 13 shows the recommended drive circuit for the acpl-m75l for optimal common-mode rejection perfor- mance. two led-current setting resistors are used instead of one. this is to balance the common mode impedance at led anode and cathode. common-mode transients can capacitively couple from the led anode (or cathode) to the output-side ground causing current to be shunted away from the led (which can be bad if the led is on) or conversely cause current to be injected into the led (bad if the led is meant to be off ). figure14 shows the parasitic capacitances which exists between led anode/cathode and output ground (c la and c lc ). also shown in figure 14 on the input side is an ac-equivalent circuit. table 1 indicates the directions of i lp and i ln fl ow depend- ing on the direction of the common-mode transient. for transients occurring when the led is on, common-mode rejection (cm l , since the output is in the low state) de- pends upon the amount of led current drive (i f ). for con- ditions where i f is close to the switching threshold (i th ), cm l also depends on the extent which i lp and i ln balance each other. in other words, any condition where common- mode transients cause a momentary decrease in i f (i.e. when dv cm /dt>0 and |i fp | > |i fn |, referring to table 1) will cause common-mode failure for transients which are fast enough. likewise for common-mode transients which occur when the led is off (i.e. cm h , since the output is high), if an im- balance between i lp and i ln results in a transient i f equal to or greater than the switching threshold of the optocou- pler, the transient signal may cause the output to spike below 2v (which constitutes a cm h failure). by using the recommended circuit in figure 13, good cmr can be achieved. the resistors recommended in figure 13 include both the output impedence of the logic driver cir- cuit and the external limiting resistor. the balanced i led - setting resistors help equalize the common mode voltage change at anode and cathode to reduce the amount by which i led is modulated from transient coupling through c la and c lc .
cmr with other drive circuits cmr performance with drive circuits other than that shown in figure 13 may be enhanced by following these guidelines: 1. use of drive circuits where current is shunted from the led in the led off state (as shown in figures 15 and 16). this is benefi cial for good cm h . 2. use of typical i fh = 6ma per datasheet recommendation using any one of the drive circuits in figures 15-17 with i f = 6 ma will result in a typical cmr of 10 kv/s for acpl- m75l, as long as the pc board layout practices are fol- lowed. figure 15 shows a circuit which can be used with any totem-pole-output ttl/lsttl/hcmos logic gate. the buff er pnp transistor allows the circuit to be used with logic devices which have low current-sinking capability. it also helps maintain the driving-gate power-supply cur- rent at a constant level to minimize ground shifting for other devices connected to the input-supply ground. when using an open-collector ttl or open-drain cmos logic gate, the circuit in figure 16 may be used. when using a cmos gate to drive the optocoupler, the circuit shown in figure 17, where the resistor is recommended to connect to the anode of the led, may be used. gnd 2 v dd2 0.1f gnd 1 r total = 300 - for v dd =3.3v = 580 - for v dd =5v 1/2r total 1/2r total v dd1 shield v o 74ls04 or any totem- pole output logic gate figure 1 3 . recommen d e d d rive circuit for acpl-m75l for high-cmr gnd 2 v o v dd2 0.1f ? r total shield ? r total i ln i lp c lc c la 15pf 530 3 1 2n3906 (any pnp) v dd 74l504 (any ttl/cmos gate) acpl-m75l led figure 1 4 . ac equivalent of acpl-m75l figure 15. ttl interface circuit for the acpl-m75l families.
for product infor m ation and a co m plete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trade m arks of avago technologies in the united states and other countries. data subject to change. cop y right ? 2005-2012 avago technologies. all rights reserved. av02-0963en - august 15, 2012 figure 1 6 . ttl open-collector/open d rain gate d rive circuit for acpl-m75l families. figure 17. cmos gate d rive circuit for acpl-m75l families. figure 18. test circuit for common mo d e transient immunity an d typical waveforms. v cm 0.1f r limit shield i f a b + - pulse gen. v o gnd2 o v (min.) v dd 0 v switch at a: i = 0 ma f switch at b: i = 6 ma f cm v h cm cm l o v (max.) cm v (peak) v o 530 3 1 v dd 74hc00 (or any open-collector /open-drain logic gate) acpl-m75l led 530 3 1 v dd 74hc04 (or any totem-pole output logic gate) acpl-m75l led

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